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Reset vector

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In computing, the reset vector is the default location a central processing unit will go to find the first instruction it will execute after a reset. The reset vector is a pointer or address, where the CPU should always begin as soon as it is able to execute instructions. The address is in a section of non-volatile memory (such as BIOS or Boot ROM) initialized to contain instructions to start the operation of the CPU, as the first step in the process of booting the system containing the CPU.[citation needed]

Examples

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Below is a list of typically used addresses by different microprocessors:

x86 family (Intel)

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  • The reset vector for the Intel 8086 processor is at physical address FFFF0h (16 bytes below 1 MB). The value of the CS register at reset is FFFFh and the value of the IP register at reset is 0000h to form the segmented address FFFFh:0000h, which maps to physical address FFFF0h.[1]
  • The reset vector for the Intel 80286 processor is at physical address FFFFF0h (16 bytes below 16 MB). The value of the CS register at reset is F000h with the descriptor base set to FF0000h and the value of the IP register at reset is FFF0h to form the segmented address FF0000h:FFF0h, which maps to physical address FFFFF0h in real mode.[2] This was changed to allow sufficient space to switch to protected mode without modifying the CS register.[3]
  • The reset vector for the Intel 80386 and later x86 processors is physical address FFFFFFF0h (16 bytes below 4 GB). The value of the selector portion of the CS register at reset is F000h, the value of the base portion of the CS register is FFFF0000h, and the value of the IP register at reset is FFF0h[4] to form the segmented address FFFF0000h:FFF0h, which maps to the physical address FFFFFFF0h in real mode.[5][6]

Others

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  • The reset vector for ARM processors is address 0x0[7][8] or 0xFFFF0000.[9] During normal execution RAM is re-mapped to this location to improve performance, compared to the original ROM-based vector table.[10]
  • The reset vector for MIPS32 processors is at virtual address 0xBFC00000,[11] which is located in the last 4 Mbytes of the KSEG1 non-cacheable region of memory.[12] The core enters kernel mode both at reset and when an exception is recognized, hence able to map the virtual address to physical address.[13]
  • The reset vector for PowerPC/Power ISA processors is at an effective address of 0x00000100 for 32-bit processors and 0x0000000000000100 for 64-bit processors.
  • The reset vector for SPARC version 8 processors is at an address of 0x00000000;[14] the reset vector for SPARC version 9 processors is at an address of 0x20 for power-on reset, 0x40 for watchdog reset, 0x60 for externally initiated reset, and 0x80 for software-initiated reset.[15]
  • The reset vector for 68000 processor family is 0x00000000 for Initial Interrupt Stack Register (IISR; Not really a reset vector and is used to initialize the stack pointer after reset.) and 0x00000004 for initial program counter (reset).[16]

8-bit processors

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  • The reset vector for 6502 processor family is a 16-bit address stored at 0xFFFC and 0xFFFD.
  • The reset vector for 6800 and 6809 processor families is a 16-bit address stored at 0xFFFE and 0xFFFF.
No Reset Vector
  • For 8051 / 8080 / 8085 / Z80, reset starts code execution at address 0x0000.
  • For AVR, reset starts code execution at address 0x0000; often a Relative Jump instruction (RJMP) is placed here to jump to the reset handling routine within the bottom 4K of memory.
  • For PIC, reset starts code execution at address 0x0000.

See also

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References

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  1. ^ "iAPX 86,88 User's Manual" (PDF). Intel. 1981. System Reset, p. 2-29, table 2-4. Retrieved April 15, 2018.
  2. ^ "AMD 80286 Datasheet" (PDF). AMD. 1985. p. 13. the 286 begins execution in real mode with the instruction at physical location FFFFF0H.
  3. ^ "iAPX 286 Programmer's Reference Manual" (PDF). Intel. 1983. Appendix D, iAPX 86/88 Software Compatibility Considerations, p. D-2. Retrieved April 15, 2018. After reset, CS:IP = F000:FFF0 on the iAPX 286. This change was made to allow sufficient code space to enter protected mode without reloading CS.
  4. ^ "80386 Programmer's Reference Manual" (PDF). Intel. 1990. Section 10.1 Processor State After Reset, pages 10-1 - 10.3.
  5. ^ "80386 Programmer's Reference Manual" (PDF). Intel. 1990. Section 10.2.3 First Instruction, p. 10-4. Retrieved November 3, 2013. Execution begins with the instruction addressed by the initial contents of the CS and IP registers. To allow the initialization software to be placed in a ROM at the top of the address space, the high 12 bits of addresses issued for the code segment are set, until the first instruction which loads the CS register, such as a far jump or call. As a result, instruction fetching begins from address 0FFFFFFF0H.
  6. ^ "Intel® 64 and IA-32 Architectures Software Developer's Manual" (PDF). Intel. May 2012. Section 9.1.4 First Instruction Executed, p. 2611. Archived from the original (PDF) on 2012-08-08. Retrieved August 23, 2012. The first instruction that is fetched and executed following a hardware reset is located at physical address FFFFFFF0h. This address is 16 bytes below the processor's uppermost physical address. The EPROM containing the software-initialization code must be located at this address.
  7. ^ "5.9.1. Vector Table and Reset". Cortex-M3 Technical Reference Manual. Retrieved 2017-11-10.
  8. ^ "Table 4-11 AArch64 reset registers". CortexARM Cortex-A72 MPCore Processor Technical Reference Manual r0p3. Retrieved 2024-01-30.
  9. ^ "Documentation – Arm Developer". developer.arm.com. Retrieved 2024-06-21.
  10. ^ "Boot sequence for an ARM based embedded system -2 - DM". www.embeddedrelated.com. Retrieved 2017-11-10.
  11. ^ "MIPS32 Architecture For Programmers; Vol III: The MIPS32 Privileged Resource Architecture" (PDF). MIPS Technologies.
  12. ^ Noergaard, Tammy (2005-02-28). Embedded Systems Architecture: A Comprehensive Guide for Engineers and Programmers. Elsevier. ISBN 9780080491240.
  13. ^ "MIPS32 M4K Processor Core Software User's Manual" (PDF). cdn2.imgtec.com. August 29, 2008. Archived from the original (PDF) on 2017-08-26.
  14. ^ The SPARC Architecture Manual, Version 8. SPARC International. p. 75.
  15. ^ The SPARC Architecture Manual, Version 9. SPARC International. pp. 109–112.
  16. ^ Labrosse, Jean J. (2008). Embedded Software. Newnes. ISBN 9780750685832.
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